NiosII/f fitting into UP3 and the leading zero tut

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originally posted by kalle leo@May 15 2006, 06:03 PM

well, the number of m4k-blocks depends largely on the cache size. maybe if you reduce data- or instruction cache you can fit the design. also have a look at the jtag debug level for the nios, maybe you can save some blocks there, too.

regarding the other problem, do you have the two timers sys_clk_timer and high_res_timer in your design? seems they are missing or maybe renamed or something.

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I&#39;ve manage to generate Fast version of NiosII system with sram and only 1Kbyte Data cache/ 4Kbyte Instruction cache. Thanks for good advices.

When I change to 2Kbyte Data cache, it didn&#39;t fit.

But my question is when I looked up compilation report for the 1Kbyte data cache system, it use only less than 50% of LEs(logic elements). Then still have more than half of resources, how it can&#39;t generate 2Kbyte data cache system?

Could you give me some more explaination, please?