NiosII with Altera SDRAM controller performance

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So we have to forget burst access, and look at pipelined read transfer.

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I don't believe this is accurate and I agree with your friends who suggested using bursts.

While the SDRAM component itself does not implement a burst slave port, Qsys will automatically generate an adapter for you.

You may enjoy reading https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/qsys_optimize.pdf

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Altera recommends that you design a burst-capable slave interface if you know that

your component requires sequential transfers to operate efficiently. Because SDRAM

memories incur a penalty when switching banks or rows, performance improves

when SDRAM memories are accessed sequentially with bursts.

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