Hi @Timothy_Adegbite,
Apologies for the delay in response due to the long holidays in our site last week.
For the mention to simulate both the Nios V processor (with your C code) and your custom VHDL module in one integrated Questa simulation.
Would suggest to add the NIosV system normally in platform designer, followed by exporting the files from quartus. You can than compile the design in Questa by vsim command (Note: you may edit the msim_setup.tcl to include your VHDL file manually if it wasn't added to platform designer) and then compile the software side of things at NiosV using the elf2hex (e.g., elf2hex --input=your_app.elf --output=app.hex --base=0x0 --end=0x1FFFF)
Hope that clarify.
Best Wishes
BB