Honored Contributor
Honored ContributorHello All,
I received a question from a forum member with the exact location of the files: It is under the "Demonstrations" Subdirectory "DE0_CV_SDRAM_Nios_Test". Last week, after many months of silence, i was happy to receive some feedback from Altera themselves regarding this issue. This as the feedback to the fact that i submitted my project for further investigation. They also concluded that there was a problem with the PLL Settings. What they did not conclude was that the basic culprit seemed to be a faulty component in the altera university blocks at that time. My conclusion: be careful with the <System and SDRAM Clocks for DE-series Boards> clock. What i would advise is to use the PLL from the ALTERA Basic functions and copy the settings from the demo board CD to the standard Altera PLL. This is also the Terrasic proposal of doing things not the solution from altera university documents. Best regards, Johi.
