Honored Contributor
Honored ContributorKevin,
The Nios II examples, for the Cyclone II DSP boards, are all based on using only 64MB of the available 256MB. Nios II's implementation of GCC includes a CALL instruction with a destination address that can span no more than 256MB. SOPC Builder flags this as an error (or warning) because the GCC toolchain could break. Your best bet, to get up and running on 5.1 in a timely fashion, is to place the PTF, QPF, and QSF, for the project that you're interested in building, in a new directory, re-generate your SOPC Builder system and re-compile in Quartus II.... Additionally, you may have to remove and add the DDR2 component into the system, using the latest DDR/DDR2 core (has to be supported by QII 5.1!). The DDR2 MegaWizard's default, of 256MB, for this DIMM, will not work in an SOPC Builder system. You need to change this default to 64MB. Best of luck! - slacker P.S.: If you just want to attempt to run some software, on an existing 5.0 design, you should be able to: 1. Program the FPGA using one of the included project's SOFs. 2. Open the Nios II IDE up, directly. 3. Follow the rest of the instructions, with the caveat that you'll have to add the path(s) to the HW project's PTF, manually. EDIT FOLLOWS: NOTE: Only the Nios II instruction master has this 256MB limitation. The data master can be connected to anything up to 2GB address span. If you want to get going, you can keep the default 256MB address span, but only connect the DDR2 to the Nios II's data master.
