NIOSII error when updating to Quartus II v5.1

There is a restriction of 256MB on Nios II instruction master is due to the jumping distance (the jump instructions can jump up to an addresses 26 bits away so 2^26 * 4(bytes/word) = 256MB)

It's been a while but I could have sworn we used one quarter of the address range of the DDR2 on that board so that the range was small enough. Could you let me know via email which design you have seen this issue with (name of the design). Also did you modify this design in any way (if so what did you change?). Judging by the address range you are seeing some addressing settings were wiped out (we reduced the number of DDR rows to reduce the address range by a factor of 4 if I remember correctly)

I hope in some way that explains what you are seeing.