Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- Is the data and instruction master set to On-Chip Memory, have you assigned the clock correctly, does the jtag-uart slave is connected to the data master of the nios along with the interrupt. Check for Qsys system correctness. No warnings or errors. --- Quote End --- Yes, I have a Qsys that is correctness compliant. All the points that you are mentioning are properly connected. 0 errors and 0 warnings.