NIOSII addressing for 32 bit wide SDRAM

Sigh. :(

The next step for me was to go to a half rate implementation which means

for my 32 bit DDR2 that the local data width is 128-bit operating at 75MHz with

DDR still at 150MHz. Timing is all met.

Ok, so I implement a variation of the solution in my last post now using a 128 bit

onchipmem and also 128 bit DMA controller so now BE = 0xFFFF for all writes/reads.

Data is getting in and out of onchipmem fine.

DMA writes look good on the local interface.

For the DMA reads it looks like the command is correct going to the controller on the local interface but the readdatavalid looks out of whack asserting and deasserting in a periodic

fashion. seemingly unrelated to the read command just sent to it and this naturally has

dire consequences to the latched data.

Searched through the forum, looked at http://www.altera.com/literature/rn/rn_ip.pdf,

looked at unsupported features.

Thoughts?