NIOSII addressing for 32 bit wide SDRAM

Still no resolution to this :(

Here is some more data...

(sorry about the screwed up formatting in the table here)

For writes(B = byte, L = local):

ACCESS BADDR BDATA LADDR BE WDATA

1 0 1 0 0F 0000000100000001h

2 4 2 0 F0 0000000200000002h

3 8 4 1 0F 0000000400000004h

4 c 8 1 F0 0000000800000008h

5 10 10 2 0F 0000001000000010h

6 14 20 2 F0 0000002000000020h

...

Behavior for reads is same but at the time of local_rdata_valid

the data on local_rdata is:

ACCESS local_rdata

1 0000000400000004h

2 0000000400000004h

3 0000000800000008h

4 0000000800000008h

5 0000004000000040h

6 0000004000000040h

...

For all these:

local_size = 1

Clearly not a fabric issue.

Issue must reside in controller(and/or the way it is configured)

or in my hardware. From here on I will only test with x4 addressing.

Currently, I am doing all the writes and then all the reads but if I do the writes and reads back to back then it works ... temporarily.

ie. if I go write,write,write,... then read,read,read,... then no good

if I go write,read,write,read, ... then ok (until I read 'em all after this)

So, it would seem that subsequent writes are stepping on the previous writes.

When I do x8 accesses BE is always 0x0F and when I do x4 accesses then BE

alternates between 0x0F and 0xF0 as expected and I think it is when I mix these two types of accesses that things go awry.

If I do x8 accesses starting at addr 0(ie. 0,8,0x10,0x18, etc) then _nothing_ gets

stomped on.

If I do x8 accesses starting at addr 4(ie. 0,4,0xC,0x14, etc) then _nothing_ gets

stomped on.

However, it is when I do writes where some use BE 0x0F and others use BE 0xF0 then that is when things go awry.

I will clarify for you how the hardward is hooked up:

o I have two 16 bit DDR2 devices.

o The same address bus goes to both DDR A0-A12

o The same BA goes to both DDR BA0-BA2

o The same CK/CK# go to both DDR CK/CK#

o The same CS,WE,RAS,CAS go to both

o DQS0,1 go to device 0 LDQS,UDQS and DQS2,3 go to device 1 LDQS,UDQS

o ODT is also shared

o DQ0-15 go to device 0, DQ16-31 go to device 1.

o LDM,UDM for both devices is grounded through a resistor.

Of course, the controller is configured as a 32 bit single device

with 1 CS, 8 DQ per DQS, drive DM pins=NO, 1 output clk pair.

Thanks.