Altera_ForumHonored Contributor15 years agoNIOSII addressing for 32 bit wide SDRAM Hello, first time poster here. As the title suggests, I have an FPGA accessing a 32 bit wide DDR2 device (actually 2x 16 bit devices with appropriately shared signals). Using SOPC builde...Show More
Altera_ForumHonored Contributor15 years agoHas anyone had this same experience as in my post# 10? Thank-you.
Recent DiscussionsFPGA Community EnqueriesLPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 ProMultiple NIOS V ImplementationSolvednot able to use multiple niosV cores at the same timeNios V/m JTAG run‑control HALT fails — Debug Module healthy, hart never halts