NIOSII addressing for 32 bit wide SDRAM

Thanks again, BadOmen.

On the topic of timing closure: I have noticed even for

clk to clk transfers that some designers use constraints such as set_max_delay to fix the

offending constraints. Is this good practice or are we just asking for trouble and should

this only be done as a last resort?

Or should, as you say, procedures such as HDL modifications, architectural changes,

or Quartus settings tweaks(for small TNS) be explored first?

>>>you could probably just do some Quartus II setting tweaks to meet timing.

Perhaps using the Quartus tool "advisors" for this or are they not so good?

Perhaps if the violation count is low then one might opt for constraining the few violating

paths but in my case there are too many to count so probably I need to either lower

the clock speed or make some architectural changes and not even think about trying to

constrain with say set_max_delay, eh? Or perhaps entertain a faster part (ie. -4)?

Thoughts?

Regards.