NIOSII addressing for 32 bit wide SDRAM

Thanks for the reply, BadOmen.

As mentioned:

>>Using SOPC builder to generate a simple system with mainly NIOSII/f and one

>>HPCII DDR2 controller.

Would you recommend trying to close timing on this project before anything else though?

If so, if I am going to run this thing at 200MHz with a -6 ArriaIIGX then perhaps

I need to alter the HDL indirectly through SOPC changes(either parametric for the given

current components or architecturally by for example adding a pipelining bridge) as

"Report Timing" in Timequest shows a number of violations(neg slack) even for clk

to clk transfers(ie. launch and latch clock are the same). Hints here?

SignalTap of use here also versus setting up sims?

Your thoughts?

Regards.