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Do you have a push button or FPGA reset that you can use at top level? I am concern with the jtag_debug_module_reset_output driving the clock source IP. Can you instead export the clk_in_reset? Probably you can use the System >> Create Global Reset Network for correctly hooking up the jtag reset output.
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@ mikedsouze: I've followed your suggestions.
- I've exported the clk_in_reset
- I've created a global reset network.
- See attachment qsys_reset_export_system_generated_reset_netw.png
- I've updated my verilog code
assign nios_reset = KEY;
nios_4b_qsys NIOS2
(
.clk_clk(clk), //, // clk.clk
.reset_reset_n(nios_reset) // reset.reset_n
);
And now it works in normal mode!!!
Not after the first download when I press the run button in eclipse, but when I press the key that is connected to the nios_reset signal in my code.
Thanks a lot mikedsouze
@fredbk: Thanks for the suggestion for using a PIO with a LED.
The PIO would be my next IP to add to my nios system.
Using it as a watchdog is very helpfull.
Rgds,
Kimberley
Honored Contributor
