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Altera_Forum
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10 years ago

Nios/e prints only in eclipse debug mode on jtag-uart, not in eclipse 'normal' mode

Hi, I'm using the C5 Soc Kit from terasic. http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=205&no=816 I have created a Nios system with qsys in q13.1 (on wi...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Do you have a push button or FPGA reset that you can use at top level? I am concern with the jtag_debug_module_reset_output driving the clock source IP. Can you instead export the clk_in_reset? Probably you can use the System >> Create Global Reset Network for correctly hooking up the jtag reset output.