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Altera_Forum
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14 years ago

nios2 processor non responsive

Hello everyone. I have created a design in SOPC builder with a NIOSIIf core which has a MMU. The SOPC file for the same is here (https://docs.google.com/open?id=0b8b-p7uizx09ztfmnwi0ntqtmdcyni0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Oh okay, I didn't know that option. In that case you are right, the derive_pll_clocks should be sufficient and you don't need to create the clocks in the sdc file.

What frequency are you generating from the pll?

It seems that most of your timing violations are on paths between the CPU and the DMA component (the "top failing paths" in Timequest is very useful for that). Try to add an Avalon Memory Mapped Pipeline Bridge between the CPU and the DMA component and see if this helps.