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Altera_Forum
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10 years ago

Nios2 gen2 interrupts getting disabled

I have just ported a project that's been working for years with a Nios2-gen1 processor to the new Nios2-gen2. Everything seems to be working fine except for one strange problem, I'm finding my interrupts are getting spontaneously disabled for some reason.

In debugging this, I've found that occasionally when an interrupt occurs (from the internal interrupt controller) the estatus register is zero. estatus should have a copy of the status register at the time of the interrupt, and since the interrupt can't occur if bit 0 of the status register is clear, then I would never expect estatus to be zero on entry to an interrupt.

I've checked the exception register and it indicates that the cause of the interrupt is the IIC, so it's definitely a hardware interrupt causing the exception.

Does anyone know if this is a known errata on the Nios2-gen2 processor?

For the moment I'm just forcing estatus to 1 in my interrupt handler, but I'd love to know what the root cause of this issue is.

Thanks,

Steve

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I have seen some kind of similar issue. But reverted to use normal data master.

    Can you try with data master?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    OK, I got a reply to the service request I submitted to Altera on this. Turns out it's a known bug with the Nios2-gen2 processor as of Quartus 15.0. They have a patch which is supposed to fix it, and will have it fixed in a future Quartus release. I'm still waiting on the patch file, so can't confirm if it fixes the problem

    And yes, it appears that the tightly coupled data master port is part of the problem. I don't have much more detail then that though.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    OK, I got a reply to the service request I submitted to Altera on this. Turns out it's a known bug with the Nios2-gen2 processor as of Quartus 15.0. They have a patch which is supposed to fix it, and will have it fixed in a future Quartus release. I'm still waiting on the patch file, so can't confirm if it fixes the problem

    And yes, it appears that the tightly coupled data master port is part of the problem. I don't have much more detail then that though.

    --- Quote End ---

    so this only happen in gen2 processor only?
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    quite interesting, the interrupt should not just disable by it self for normal usage, as it was not happening my side. Do you have any other component or item that in usage that may trigger that special disable event?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    I think it's just a bug in the Nios2 processor generator shipped with Quartus 15.0. It seems to have something to do with the tightly coupled data master port.

    Altera support was able to quickly provide a patch when I put in my service request, so they appear to know about it. I asked for a list of know bugs in the Nios processor, but they were not able/willing to provide one.

    Quartus 15.1 has now been released, so I would expect that this bug has now been fixed in the software.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    and i also wondering why the 15.1 and 15.0 version is quite close in term of release date. just a few months in between.. maybe too much bugssSSSSSS :D

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    This is interesting that you are having this issue as well.

    About a month ago, I was working on a design where the IRQ was not being recieved by the NIOS.

    If I implemented the NIOS as a sub Qsys system, it would not work.

    If I implemeted the NIOS as a stand alone Qsys system, it would work.

    ienable and the status register were always 0 and could not be written to in the "sub-system case".

    The issue was solved by using an IRQ bridge.

    Sounds like there are a few Nios IRQ issues out there.