Nios2: DMA+FIFO

Thank you for the answer, BadOmen. All data widths for DMA are enabled (byte,halfword,word...). I'll try using two ioct commands but it seems RCON is OK. I'm working on ethernet interface based on wiz820io module, so I have to reorganize received bytes that form TCP packets into a bit stream. I've also considered using DMA and external fifo, but byte duaration on DMA output varies from 1 clk period to 3 clk periods, so it's impossible to write data correctly into fifo. As regards SGDMA I don't think I need such complicated component cause I'm only going to realize 100Mbps Ethernet and I'm trying to be economical with FPGA resources.