nios2 + 8GB DDR3 /DDR3 SDRAM Controller with UniPHY

You see, after some haggling to erase the other errors, the remaining are one for each NIOS: "Address width above 32 bits are not supported for Nios II".

So QSYS with NIOS is limited to 32 bit addressing internally no matter what.

I tried building a subsystem but it seems QSYS does not treat subsystems any differently, it's just a visual aid.

What I ended up doing is to write them out as two separate qsys blocks and then join them through a pipeline bridge through verilog/top.

Let's see if it works!