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Altera_Forum
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10 years ago

nios2 + 8GB DDR3 /DDR3 SDRAM Controller with UniPHY

I'm trying to finish a simple test with a nios2/f + 1Mb on-chip memory + DDR3 controller. The DDR3 controller is connected to 8Gb DDR3 controller, which I took straight from the board manufacture...
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Altera_Forum
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10 years ago

Hi Mike,

Thank you. I think that's exactly what is needed.

However when I add all those to the *same* qsys project, it still complains about the address range. I believe qsys uses the biggest address range as a parameter so therefore I will have to break this down into two or more qsys projects.

Is making the NIOS a subsystem of the main project a solution? Is there any way to accomplish this inside qsys without having to rewire everything through verilog/top?