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Altera_Forum's avatar
Altera_Forum
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10 years ago

NIOS with 2Gb SDRAM

Hi all,

I have come across some problems using NIOS in my project. here is the background:

I have a 2Gb DDR2 for the NIOS to run on. I have build the Qsys and connected all components. but when I tried to assign the address, I got the "instruction master only support 28 bit address" warning. because if I assign 0x00000000 ~ 0x0fffffff to the SDRAM controller, then I have to assign 0x10000000 to the JTAG_debug_module; if I assign 0x00000000 to the JTAG_debug_module, then I have to assign 0x10000000 ~ 0x1fffffff to the SDRAM controller. Either way I still got the warning. so, I have add a "direct window bridge" between the instruction master and the SDRAM controller:

http://www.alteraforum.com/forum/attachment.php?attachmentid=10920&stc=1

and the address:

http://www.alteraforum.com/forum/attachment.php?attachmentid=10921&stc=1

the direct window bridge module I was downloaded from the Alterawiki. I have modify the TCL file, setting the module as a memory device. and then I modify the linker section settings in the BSP setting to separate the data and instruction:

http://www.alteraforum.com/forum/attachment.php?attachmentid=10922&stc=1

after all I tried to run my code. I can successfully download the NIOS software, but it looks like the code is not running at all. I can not even debug with the code.

I am not sure I have done everything correctly or I have missed something important. I am looking forwards to your suggestions, thanks a lot!

Best Regards

Daniel

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    .text and .exceptions will contain NIOS instructions. Your linker script shows .text being placed into 'data_memory' Shouldn't it be placed in 'direct_window_bridge_0'

    edit:

    Also, the Qsys warning (at least on 12.1) is:

    --- Quote Start ---

    Warning: System.nios2_qsys_0: The address range of the slaves connected to the Nios II instruction masters exceeds 28 bits. Attempts to call functions across 28-bit boundaries is not supported by GCC and will result in linker errors.

    --- Quote End ---

    It isn't saying you can't connect the instruction master to a memory wider than 28 bits. It's saying you can't have instructions located on either side of a 28-bit boundary and expect it to work.

    So I think much of your work was not necessary?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    hi Ted,

    thanks for reply.

    because of the limitation of the address assignment, the start address of the SDRAM controller or the JTAG_DEBUG_MODULE must exceed 28 bits. to my understand, one of the two module will not work.

    anyway, I will try with your suggestion first to remove the direct window bridge first, and I will assign 0x00000000~0x0fffffff to the sdram controller and 0x10000000 to the JTAG_DEBUG_MODULE.

    BR

    Daniel
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I would suggest to disconnect the cpu.data_master/altmemddr_0.s0 and connect the cpu.data_master to the direct_window_bridge_0 so that the data_master has the same "view" with the instruction master.

    In your linker region the data_memory is located at 0x1400_0000 to 0x1fff_ffff. How can the instruction runs since it is still pointing to 0x1000_0000?