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tcmichals_home's avatar
tcmichals_home
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2 years ago

NIOS V/g version 1.0 vs 2.0 Atomic instruction

Using NIOS/g 1.0 the following code works:

00001604: lw a5,-20(s0)
00001608: lw a4,-24(s0)
0000160c: fence iorw,ow
00001610: amoswap.w.aq zero,a4,(a5)

Using NIOS/g 2.0 an exception occurs when 1610 executes, amoswap. The mcause register value is 2, stating it is an illegal instruction.

Recompile the code, did not fix issue. Validated the memory location is accessible.

According to the web site, A (atomic instructions should be supported). The API C/C++ API is std::atomic<uint32_t> value being updated.

_GLIBCXX_ALWAYS_INLINE void

store(__int_type __i, memory_order __m = memory_order_seq_cst) noexcept

{

memory_order __b __attribute__ ((__unused__))

= __m & __memory_order_mask;

__glibcxx_assert(__b != memory_order_acquire);

__glibcxx_assert(__b != memory_order_acq_rel);

__glibcxx_assert(__b != memory_order_consume);

__atomic_store_n(&_M_i, __i, int(__m)); <--- the function calling the fence/swap

From https://www.intel.com/content/www/us/en/docs/programmable/683632/23-4/processor-73511.html the processor should support Atomic instructions. Version 1.0 did.

Tim

Embedded Applications Layer

8 Replies

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Unfortunately, our Nios V currently does not support Atomic instruction yet.


    I will channel this to our internal team as feedback request.


    Is there any other questions from your side?


    • tcmichals_home's avatar
      tcmichals_home
      Icon for New Contributor rankNew Contributor
      2 years ago

      Issue resolved.

      niosv-bsp-editor needs to be updated to remove atomic support from compiler option

  • tcmichals_home's avatar
    tcmichals_home
    Icon for New Contributor rankNew Contributor
    2 years ago

    OK, looking see link:

    • RV32IAZicsr (Pipelined) & RV32IZicsr (Non-Pipelined)

    Another web has:

    States:

    • Pipelined
      • Applies RV32IZicsr instruction set.
      • Supports five-stages pipeline datapath.
    • Non-pipelined
      • Applies RV32IZicsr instruction set.
      • Supports non-pipeline datapath.

    This post is having the same issue.

    So, Atomic is not supported? Or is it?

    • tcmichals_home's avatar
      tcmichals_home
      Icon for New Contributor rankNew Contributor
      2 years ago

      according to the toolchain.cmake generated by niosv-bsp-editor there is -march=rv32ia this should be rv32i if the processor does not support Atomic. Using this option the code now works.

  • Kevin26's avatar
    Kevin26
    Icon for New Contributor rankNew Contributor
    2 years ago

    That's what I changed also but your original question about does the RISC V/m Pipelined and RISC V/g support atomic instructions is still valid. The documentation says it should.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Thank you for your feedback, I will check that out and send this feedback to our internal team as feedback request to make the proper changes.


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    Thanks for your feedback, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.