Nios V Hardware Interrupt Limitations

Hello,

Thank you for your response.

I initially understood that the IRQ Bridge could be used as a multiplexing mechanism to connect multiple interrupt sources to a single IRQ line on Nios V. However, after reviewing its configuration, it seems that the IRQ signal width must be set to match the exact number of sender IRQs, meaning it does not dynamically multiplex interrupts.

For example, if I set the IRQ signal width to 2, the receiver_irq port becomes 2 bits wide (receiver_irq[1:0]), and exactly two interrupt sender ports (sender0_irq and sender1_irq) are created. If I then try to connect a third interrupt source, Platform Designer throws an out-of-range error, preventing me from adding more sources than the set width allows. This suggests that the IRQ Bridge does not act as an interrupt multiplexer in the way I originally assumed.

Based on the link that you shared, The IRQ Bridge Intel FPGA IP allows us to route interrupt wires between Platform Designer subsystems.

Given that Nios V has a limited number of IRQ lines and does not support an external interrupt controller, how do you expect us to use the IRQ Bridge to overcome these limitations? If the IRQ Bridge does not support dynamic multiplexing, is there another recommended approach for handling more interrupts than the CPU natively supports?

One possible solution would be to develop a custom interrupt bridge that aggregates different interrupts into a register and generates a single interrupt for the processor when any of the sources become active. The processor could then access this register via the Avalon interface to determine the original interrupt source. However, we would like to know Intel’s recommended approach for handling this scenario.

Best regards.