NIOS SDRAM performance

Clancy,

[list][*]I'm not doing random reads. My tests were performing a memcpy, these are consecutive reads. So no RAS cycle except if bank/row needs to be changed.

[*]I use stwio/ldwio instructions. These are cache-bypass instructions, so the data cache must not have a performance impact. There cannot be some cycle penalty "until a rquest hits the Avalon bus".

[*]There are almost no cycle penalties (I guess one or two) to get requests out to the SDRAM. You can see consecutive SDRAM writes, so all cycles necessary to get a request from NIOS to SDRAM are "hidden" in the time the SDRAM controller needs to select bank/row and initiate the write (the SDRAM controller has a pipleine that can store a few requests)

[*]If a request is passed to the SDRAM, it needs one cycle to crank out the response, at least if no bank/row needs to be changed. Just put the new address on the bus, and set the control signals (RAS, CAS, CS, WE) to READ.

[*]The next instruction (no matter whether it is cached or not) is already in the pipeline (which is stalled until the response arrives), so no cycle penalty to get the next instruction (at least if NIOS does not FLUSH it's pipeline, but IMO there should be no reason for it).

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Additionally, we are in contact with Altera support since more than 3 months about this issue (through our support here in Germany) and they still did not tell us an officical statement about the reasion / planned fix for this... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

Dirk