NIOS SDRAM performance

Jesse,

Any progress in your talks with your CPU Expert?

This is really important stuff. 2-3 cycles expected vs. 12 cycles is death for many applications. (including mine)

And the biggest/scariest problem is that this info has to come out only after monumental efforts by people like Dirk.

Chapter 16 "Nios II Core Implementation Details" states that the /f core is designed to "Minimize the instructions-per-cycle execution efficiency" and for "performance-critical applications ... with large amounts of code and or/data..."

Then in the Instruction Execution Performance for the Nios II /f Core Table, LOAD has >1 as the number of cycles.

Anyway, "large amounts of code and or/data" means SDRAM these days, and although 12 cycles is technically covered by >1, the enormous penalty for SDRAM access should at least be spelled out.

What other issues like this remain un documented?

We're designing real products with real money and deserve to have this information provided. We can handle the truth we just need to know what it is.

Of course there is also the fact that if you want to compete (or want us customers to compete) with the NiosII processor we'll need to do much better than 12 cycles per read.

Sorry if this comes across as harsh. I have all the respect and appreciation for Altera and the Nios/SOPC group and wish you all and your products the greatest possible success. And I look forward to the day when I ship a Nios based product that kicks butt.

Ken