NIOS SDRAM hang up after reset

Dear Forum,

I’ve found the problem – it’s of course “homemade”. In my previous designs I used a second clk source as part of my nios setup (see the image in my previous post) however it turned out that there is no need to also feed the sdram controller with the phase shifted clk signal required for the sdram. After simply connecting the sdram controllers clk with the same clk as used for the nios reset works as expected. Just in case I am not the only one with that problem I’ve attached another screenshot of my nios setup.https://alteraforum.com/forum/attachment.php?attachmentid=14014&stc=1

what i was thinking about in my last point was that those two lineswill overwrite the reset vector, causing the system to be unbootable is the cpu has its reset vector set to the sdram. did you try without this operation?

To test sdram I executed the "hello world example" which is part of the eclipse wizard and what refused to work. The given code examples in my prev. post where only made for investigating whether the content stored inside the sdram can survive reset (which was indeed the case).

Thank you