Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Nios porting in the Altera SLS UP3 Education kit

Hye frndz,

I am getting the problem in porting of the Nios in UP3 Education kit, the problem is that when I am building the system using the Nios cpu and using the sls_ram module for this kit and after that when I am adding the Tri state bridge bus, hat time this bridge take Ram as a slave, which means master port is not connected, and due to this problem it will not generate the system.

If I will use flash in the system then it will use flash as a master , but the pin assignments of the flash data bus and conrol signal is the same according to the kit, so, it will not compile the project in Quartus5.0, That's why I am not using flash in my system.

Please if any one knows about that kit and knows the solution of the problem, then help me.

Thanx

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    May be, you should refer to the "Accessing Memory" tutorial, provided by sls. goto www.slscorp.com/up3support/pages/documents.php.

    they also give you a reference design. the design is tailored for the UP3-1C6, so if you use the UP3-1C12 refer to the different pin locations for some of the components. A document explaining the pin-differences between both boards can also be found on this page.