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Altera_Forum
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16 years ago

Nios interrupt response time

I have a custom SOPC component which has an interrupt sender (irq_n) in it's avalon interface. In my SOPC component HDL I set the irq_n line low, which causes a Nios interrupt handler to fire. In the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Me too. Just 28 cycles for nios/f +EIC+VIC+SDRAM+shadow rsgister+1K cache with 100Mhz Clock. Used to be 1600 cycle for nios/s +IIC +SDRAM with 50MHz Clock. I use the SignalTap II logic analyzer to measure the interrupt response time. Obviously EIC comes with much better performance than the IIC and could be implemented for the real time applications.