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Altera_Forum
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16 years ago

Nios interrupt response time

I have a custom SOPC component which has an interrupt sender (irq_n) in it's avalon interface. In my SOPC component HDL I set the irq_n line low, which causes a Nios interrupt handler to fire. In the...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Finally I use EIC+Shadow Register+VIC+Tightly Coupled Memory achieved a 30-90 cycles interrupt response time, which means the first instruction in the ISR is executed(finished) 30-90 cycles after the corresponding IRQ is asserted.

To make the full use of TCM, I assign the whole .exception section to TCM. Then I assign the ISR funtion and VIC vectior table to .exception section.