Nios II/f performance on Cyclone IV E

SOPC system layout is exactly the same as their (Altera) CycloneIII design

example which (they say) achieves over 150 DMIPS clocked at 140MHz.

Dhrystone app has a set of build scripts carefully specifying how to (or rather

not to) optimize the code. HW multiplier is build with embedded multipliers,

all code runs from internal RAM (dual port - one to instruction and other to

data master).

I've also tested running the same code from SDRAM - 41 DMIPS at 100MHz.

I get the same result on another design on which I run uClinux with included

dhrystone (different compiler, different program - but same dhrystone 2.1

codebase).

There is an old post about NiosII/f dhrystone on Cyclone EP1C20F400C7.

The author got 35 DMIPS at 50 MHz and Cyclone I doesn't even have

embedded multipliers. I get 31 DMIPS as 50 MHz...