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Altera_Forum's avatar
Altera_Forum
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21 years ago

NIOS II/f core

I create system design based on NIOS II/s core (insrt cahe 512 bytes). In my design programm and data memory located in SRAM (Cyc. dev board). RESET and ISR code in on_chip RAM. My program work ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Don't forget to make things like this:

alt_avalon_lan91c111_if* dev_list_ptr = (alt_avalon_lan91c111_if*)alt_ethernet_device_list.next;

volatile declerations (volatile doesn't bypass cache anymore, but it should be done still since the compiler could synthesize that out).