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Honored Contributor
Honored ContributorNIOS II/f core
I create system design based on NIOS II/s core (insrt cahe 512 bytes). In my design programm and data memory located in SRAM (Cyc. dev board). RESET and ISR code in on_chip RAM. My program work ...
Altera_ForumHonored Contributor
Honored ContributorDon't forget to make things like this:
alt_avalon_lan91c111_if* dev_list_ptr = (alt_avalon_lan91c111_if*)alt_ethernet_device_list.next; volatile declerations (volatile doesn't bypass cache anymore, but it should be done still since the compiler could synthesize that out).
