Honored ContributorHas anyone used the Nios II/f with DDR4 memory using the Arria 10 SoC dev board. I've tried and only get errors about exceeding 32 address lines. If I reduce data width from 72 to 64, then fitter complains about DQ_GRP at compile time.
Honored ContributorI've used this before and yes, you need to reduce the data width to 32 if you can connecting the Nios data master to the Arria 10 External Memory Interface IP. I am using DDR3 and reduce the DQ pins/DQS group to 8, number of DQS group will then be 4.
Honored ContributorI just started using it as well. I had to use the Address Span Extender to fix the "exceeding 32 address lines" error. However, using the span extender somehow prevents the DDR4 from showing up in the system.h file in Nios II. Did you have the same experience?
I need to access the DDR4 base address so that I can read/write to the DDR4 in Nios II.
