Nios II uClinux boot

Hi, Happy New Year to all, there is a good news I successfully generated the vmlinux and vmimage by re-installing some missing libs., but not got full success yet,

one thing that i feel not OK is that the size of vmlinux is 140.1 MB and vmimage is 4.7 MB and the SDRAM on my board is 32 MBytes, does it mean that I will be unable to boot Linux or I have to increase my SDRAM (that will we really very painful task for me, you know!)

OR in the above case can I reduce the size of vmlinux to fit in my SDRAM size, how??

OR can I use other smaller files (less than 32 MBytes) : vmlinux.bin = 10.8 MB, vmlinux.gz = 4.7 MB, vmimage = 4.7 MB to boot linux.

OR generate some other file to boot OR etc.

I am saying this because my nios2-download -g vmlinux command is not working, always the verification fails. (please see the attached images)

I am totally in dark, please help me. thanks

You can refer to the following AN/tutorial on how to use MicroC/OS-II with NIOS. The memory footprint needed for a basic uCOS system is 1K+ so depending on how you configure the system the memory footprint will vary.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/tt/tt_nios2_microc_osii_tutorial.pdf

You may refer some guidance here to get started

1) https://fpgawiki.intel.com/wiki/UClinux => Let's start it step by step

2) https://fpgawiki.intel.com/wiki/UClinuxDist, How to boot up

Hi Great thanks for all your replies, I googled and youtubed a lot and found many tutorials but as i have a custom board none matched mine.

so i decided to start from ground following the tutorials, till now i have made the Qsys system,

good news i have 32MB on board RAM h57v2562gtr-75c

but i have a confusion : the cpu is 32bit, but my RAM has only 16bit data lines, will it be a problem??

for THE components please click on the following links of my google drive,

SYSTEM : https://drive.google.com/open?id=1z08pRWrfmOHU0ZU6KEM2lCVhZDHMowMP
CPU : https://drive.google.com/open?id=1al9st1mU9bCHLoddMTswu1tsU7brI0rE
SDRAM: https://drive.google.com/open?id=1YbV4rS3poOKPFLl8U3K18TYco3-hBmaz
SDRAM_TIMINGS: https://drive.google.com/open?id=1g8-zIl1-Eu-Z5eEvC7hqLkMjbba4ejHJ
JTAG: https://drive.google.com/open?id=1bkFR47tpzvqT8USkgIpQBZ_mfYWJb16c
TIMER: https://drive.google.com/open?id=16MxmKIm-wbB0OYv4ELiyM7DwVXUDCCxT
UART : https://drive.google.com/open?id=1pipQjNQl9QLCsmlObjdgqzyoIOd7gFXG
REPORT : https://drive.google.com/open?id=1bgGNpyV5zOp8XubkuXEujGm8xdT291tk

Please have a look on the above work and please check is it OK to move further ??

waiting for your reply,

thanks in advance

thanks

Data width difference between master and slave would not have any issue. Qsys inserts width adapter in the interconnect to overcome it https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/qts/qsys_interconnect.pdf, figure 7-2