Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Nios II TSE design requires being loaded twice???

I am using a DE2-115 Cyclone IV board. For some reason, I need to upload my compiled C code a second time in order for it to work and pass network traffic. I am using a Triple Speed Ethernet d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

a_x_h_75,

I had finally figured it out after a month of troubleshooting. I thought it was timing constrains (*.sdc file) but had the same problem after correcting 200+ violations.

What was happening was I was configuring the PHY chips BEFORE setting their proper addresses (0x10 and 0x11 for the Terasic DE2-115 Cyclone IV board). In essence, the first load was configuring PHY chips that didn't exist, then stored the correct addresses for them (0x10 and 0x11). The second load completed PHY configuration.