NIOS II System & perfromance limitations

I am having some performance problems, maybe there is someone who can give me some suggestions. My system configuration is as follows :-

1. NIOS II/f CPU with 512 bytes instruction Cache, no Data Cache (I have not omitted the Data Master Port)

2. EPCS for code storage

3. 2 x external SRAM (16 x 64K) implemented via a single 32 bit custom component and registered tri-state bridge.

4. 2 custom components with their own separated tri-state bridges for a custom logic block and an external Dual Port Ram

5. 32 x 21Kbytes of on chip memory (not tightly coupled)

6. PLL producing system clock of 85 MHz.

The system did not work at 85 MHz (the code seemed to behave in a peculiar manner both in debug after Flash Programming). When I reduced the sysCLK to 70 MHz I started to get good results. I had a look at the signals to the ASRAM and it seemed to be the culprit, but I can be sure. I realized that this may be the source of the problem when I ran part of the code solely out of the On Chip Memory at sysCLK of 85MHz (the whole code does not fit – I am missing close to 10 Kbytes (21 Kbytes was the max I could compile). However, with further testing, I found that the performance of the system does not meet the requirements of our project. I tried a number of different things. I tried different settings for the linker script (dividing the instructions, read/write data, stack etc. between the external ASRAM & On Chip Memory). Nothing seemed to help. I tried different clock domains (my intension was to place the ASRAM tristate bridge clock at a lower frequency and the rest of the system at a higher frequency). The system didn’t work at all. I used the single PLL to produce a system clock of 85MHz and 70 Mhz for the ASRAM Tristate Bridge. When playing around with the Clock domains of the system, I tried different options for pipelining the clocks, but this didn’t help either.

I then thought that possibly I could speed things up by implementing the ASRAM custom component without a tri-state bridge (i.e. all signals except for clock(global) I changed to Avalon_slave). The system didn’t work at all. I have a feeling that possibly the signals still need to be registered to the ASRAM.

Does anyone have any suggestions that may help ?