Nios II simulation with Questa
Dear Support,
After few weeks struggle, finally I got the AN351 working on my Quartus Pro 21.3. I am so happy and feel surprised. there is still something not working as expected. most of the signals won't show up in the Objects window and Wave window. as in the picture.
the signal in at least one model can show in the Object window, and Wave window. you also see signal waveform.
add wave -position insertpoint sim:/niosii_system_tb/i1/ram/ram/the_altsyncram/*
the signals in most of the module would not show up. there must be some setup of the simulator or compiler wrong. it is so close to the goal. hope I can get support from this forum. To help analysis the problem, I attached the transcript.zip with the post.
add wave -position insertpoint sim:/niosii_system_tb/i1/*
# ** UI-Msg: (vish-4014) No objects found matching '/niosii_system_tb/i1/*'.
add wave -position insertpoint sim:/niosii_system_tb/i1/jtag_uart/*
# ** UI-Msg: (vish-4014) No objects found matching '/niosii_system_tb/i1/jtag_uart/*'.
add wave -position insertpoint sim:/niosii_system_tb/i1/nios2/nios2/cpu/niosii_system_nios2_altera_nios2_gen2_unit_1910_qtzlsya_ic_data/*
# ** UI-Msg: (vish-4014) No objects found matching '/niosii_system_tb/i1/nios2/nios2/cpu/niosii_system_nios2_altera_nios2_gen2_unit_1910_qtzlsya_ic_data/*'.
add wave -position insertpoint sim:/niosii_system_tb/i1/nios2/nios2/cpu/niosii_system_nios2_altera_nios2_gen2_unit_1910_qtzlsya_ic_data/the_altsyncram/*
I figured out the problem, maybe it is a question too easy to be answered. the commands Nios II Eclipse send out are
Do load_sim.tcl.
LD
Change the ld to ld_debug will make all signals show up.
finally, I think I know how this Nios II Eclipse and Questa works. I would say, AN351 as a tutorial was a failure. I will give it barely grade C if it is a high school project. maybe there is good one which I don't know. maybe I should have read the "Quartus Prime Pro Edition Handbook Volume 1 ,2, 3" and "Nios® II Software Developer Handbook" line by line.
Intel may have the best FPGA and design tools. the barrier to entry is so discourage, that is good news to who want to earn more money.