NIOS II SBT Configuration with EPCS Controller

This is starting to sounds a bit more complicated than I'd hoped!

I suppose I'd imagined that given how seemless the approach to booting from EPCS had been (good support and documentation), I'd imagined that the BST would have been 'setup' to deal with that approach.

The easiest path at the moment is probably to develop with the NIOS reset vector set to the base of the on chip memory, then change it over to the EPCS controller when I want to flash the EPCS.

Out of interest, what is the inconsistency between paddr and vaddr a sign of? I've certainly not done anything deliberate to make it that way!

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .entry        00000020  00008800  00008800  00004800  2**5
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .exceptions   00000194  00004020  00004020  00001020  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .text         00002c80  000041b4  000041b4  000011b4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .rodata       00000078  00006e34  00006e34  00003e34  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  4 .rwdata       000002e0  00006eac  0000718c  00003eac  2**2
                  CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
  5 .bss          0000011c  0000746c  0000746c  0000446c  2**2
                  ALLOC, SMALL_DATA