NIOS II SBT Configuration with EPCS Controller

Hi DSL,

Over the weekend I had a similar thought. It looks like a simple reset branch is 'trying' to be placed in the EPCS controller memory location.

Some select parts from objdump

Program Header:
    LOAD off    0x00001020 vaddr 0x00004020 paddr 0x00004020 align 2**12
         filesz 0x00002e8c memsz 0x00002e8c flags r-x
    LOAD off    0x00003eac vaddr 0x00006eac paddr 0x0000718c align 2**12
         filesz 0x000002e0 memsz 0x000002e0 flags rw-
    LOAD off    0x0000446c vaddr 0x0000746c paddr 0x0000746c align 2**12
         filesz 0x00000000 memsz 0x0000011c flags rw-
    LOAD off    0x00004800 vaddr 0x00008800 paddr 0x00008800 align 2**12
         filesz 0x00000020 memsz 0x00000020 flags r-x

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .entry        00000020  00008800  00008800  00004800  2**5
                  CONTENTS, ALLOC, LOAD, READONLY, CODE

Disassembly of section .entry:
00008800 <__reset>:
    8800:	00400034 	movhi	at,0
    8804:	08506d14 	ori	at,at,16820
    8808:	0800683a 	jmp	at

All this does make sense as to use the EPCS Controller Boot Loader you need to set the NIOS reset vector to the base address of the EPCS Controller. However, this of course makes things awkward when trying to load a binary over JTAG from the BST.

Is there anything I can do to make this work?

Thanks again

Andy