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Honored Contributor
Honored ContributorNIOS II reset
Dear everybody, My goal is to reset NIOS II. NIOS II owns the reset_n input and I drive this input with a signal ON-OFF-ON where the OFF state lasts 20 us with the clk signal always present...
Altera_ForumHonored Contributor
Honored ContributorFrom the document: You can set up the watchdog timer by writing the upper 12 bits of the 29-bit timeout
value to address 0x02 of the core. To reset the watchdog timer, set the RESET_TIMER bit of the control/status register to 1 and immediately set the bit to 0. The signal that the timer uses is called "reset_request" which gets combined with all the other resets in your system and synchronized to the various clock domains of your system. So if you don't kick the dog fast enough the timer will timeout, assert reset_request, the entire system will reset, and the reset_request will be de-asserted (and your CPU starts at the reset location).
