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originally posted by alessandro@Mar 2 2006, 10:28 AM
dear everybody,
my goal is to reset nios ii. nios ii owns the reset_n input and i drive this
input with a signal on-off-on where the off state lasts 20 us with the clk
signal always present.
what happens is that nios ii makes a reset because the software crashes, but
it never exits from this state when the reset_n input goes high again. i have to
make a fpga configuration by pulling down nconfig in order nios ii runs again.
where am i wrong ?
best regards
/alessandro
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perhaps 20us is not enough, I don't know,
I use a avalon timer and simple let it run into a
watchdog reset to reset the cpu.
avalon timer "timer_wd"
- PresetConfiguration (Custom)
- fixed period 3 sec
- enabled timeout pulse (1clock wide)
- enabled system reset on timeout
if I want to reset the whole chip I can enable an "and gate"
to let the timeout pulse from the watchdog timer trigger the
reconfig request output.