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Altera_Forum
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16 years ago

nios II processor not responding after high performance sdram controller addition

Hi all! I'm using the nios II v9.1 in my work and run my projects on the Cyclone III evalution board. It's allright if I use any design without sdram. But every time I add a high performance sdram...
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Altera_Forum
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12 years ago

Hi rennyosu,

If I understood your question, you have an SDRAM on your system using the General Clock.

If that's the case, depending on the frequency used, the SDRAM input clock has to be phase shifted so you can get the right timing for read/write operations.

In this case, the use of a PLL is required.

These two links should help you.

http://www.alterawiki.com/wiki/off-chip_memory_pll_tuning_example

http://www.alteraforum.com/forum/showthread.php?t=18949

Hope it helps!

Renato

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Hello Renato,

I have this problem and I can't find a way to solve it...I have a clock module on Qsys and then the ouput of that is connected to the reference clock....I am not sure what assignments i need to change...I would really appreciate your help.

Renato

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