Forum Discussion
Altera_Forum
Honored Contributor
16 years agoHello,
I once had problems with a DE2 Board and Sdram, cause you have to manipulate the clock phase there to get it working, but that will beside that throw a verification error I think. On the Cycl.III Board I had no problems using the ram, but you need a Clock-Crossing Bridge between CPU and DDR to get it going with high performance. Perhaps you will have to leave the programmer open, while using the big Nios to keep the core running. Have you tried besides adding the component to your design running one of the design examples from Altera with SDRAM included? Perhaps try that out, they have even a memory test application with the evaluation kit sources. In worst case your core is perhaps not running correctly on the Board. Check for errors again while compiling and check also, if you are downloading the right file. Good luck!