Honored Contributor
Honored ContributorAh! I'm very sorry I did not know that multiple triggers have to assert simultaneously. With that change I do get a trigger on write. Thank you very much for that lesson! It's been working for me up to now by shear luck!
On the memory write problem, I havn't gotten any further. I have been using the VHDL version of the core as the rest of my code is VHDL so I wanted to keep in VHDL for continuity. However, I decided to throw in the towel for now and use the Verilog version which worked almost straight away when I wired it up. My plan is to implement my application fully with the Verilog core and then maybe come back to the VHDL to try to debug. Thanks a million for your time.
