Nios II max clock speed

Thanx for the input everyone. These are very useful tips.

Jesse, the "export" signal is a very good idea. I will have to try that out. Currently my design seems very basic, I load in a bunch of data from compact flash card into sdram and then dma them continuously to an external device. This works okay since i can put in a 32 bit fifo to do some data buffering. But now they require to run at twice the data rate. The easiest choice I thought was to increase the clock speed. But now I see I can use the export port to send in a clock signal to drive the data out at twice the rate. The only problem i can see is that I require twice the amount of data in same amount of time. I guess I can increase the data width transfer size of the dma controllers to 64 bits or more into the same size fifo.

Does this sound fair? I'll have to try it out.

-Quan