Nios II max clock speed

One additional piece of advice: The numbers James quotes for Nios apply to the CPU and interfaces to onchip memory, PIO, etc. If you add an SDRAM controller you'll probably see the f-max go down as that will be the critical path (I can't give you an exact quote for Cyclone, but our SDRAM controller tops out at around 105-110Mhz in Stratix (I)).

If this does happen - and you need SDRAM in the same system as Nios - you'll need to design some logic that goes between your HDL and its Avalon interface to cross clock domains (a couple of synch. flops at the very least). The basic requirement is that user-definied logic imported to SOPC Builder have avalon port(s) which use the SOPC Builder system's clock... it is certainly legal to have an extra clock signal feeding your logic (of type "export" in the user-logic wizard).

The cyclone chip you're using should have PLL circuitry that you can use to create two clocks of the speeds you need (take a look at the standard cyclone example design if you're not familiar with the PLLs - we use two of them to drive Nios, and send a phase shifted clock off to SDRAM).