NIOS II JTAG Download errors

Just some additional info... I added a 1n/1u decoupling combo to the power pin of the header, and didn't help... also added a 10K0 pullupp to TDO. The more I think about this, it doesn't seem to be a JTAG problem... could the DDR core be locking up the NIOS processor somehow so it doesn't respond?

- I setup a test system with a nios processor and onchip RAM, and outside the NIOS processor, the Altera DDR example driver testing the DDR SDRAM. The DDR test was passing, and I could download code to the NIOS processor. This would seem to rule out a JTAG routing issue since the DDR is active, as well as the NIOS trying to download code. The only difference now is that the DDR core is separated from the processor.... does this make sense?

- Also, I setup another project where the processor and RAM were clocked by different PLLs - the processor @ 48MHz, and the DDR and 80M from separate clock inputs. I could then download to the onchip RAM and run, but when I tried to download to DDR, I got a verified fail?