Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

NIOS II Interrupt Registration

Hello, My question is with regard to using NIOS II Interrupts on a Cyclone IV E board. The NIOS II was designed using the QSYS module within quartus and a VIC was added in order to allow ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Are you sure the interrupt is actually triggered? The IRQ signal must stay high until the CPU sees it and runs the ISR. Then it should be the ISR that writes something to the component to say it can deassert the IRQ signal again.

Is your count variable defined as volatile? You should do that to prevent the compiler from running some optimisations that could hide the update done by the isr routine.