Nios II interface with pci-express

There is a PCIe slave to Avalon master block that allows a single PCIe BAR to access multiple devices via the avalon bus. This is probably slightly slower than using a BAR for a single 'slave' but much more flexible.

You might need to arrange the avalon slave addresses to reduce the address span - but we map a single 32MB BAR (16MB SDRAM + io).

Be aware that all PCIe transfers are 64bit with 8 byte enables. The bus width adapter always generates two 32bit cycles, typically one has no byte enables asserted - if your slave assumes 32bit accesses it will get confused!

You can then wite an avalon slave that can drive the Nios2 interrupt (and probably soft-rest) lines. No reason not to let the nios write as well and use a separate mask register, and maybe use 'write to set' and 'write to clear' registers to avoid read-modify-write cycles....

It will be simpler (but slower) if you do all the PCIe tranfers from the host. You'll need to get the nios to generate PCIe interrupts (we use a dedicated non-pcei interrupt), then have the host driver read a status regeister then the response (if available) - etc.

If you need more than simple requests, use 'ring buffers' since they don't require the reader and writer to have write access to the same location, but allow mutiple requests be queued.