normaly between the sdram and the nios is the sdram controller ip
this ip controls the read and write access from and to the external memory
all these accesses could be random or sequential type
why shouldn't it be possible to write the complete memory if the sdram controler ip takes care about the external sdram interface (refresh, access ... ) ???
i have done lots of designs where a couple of masters read and or write to a sdram slave memory.
if the memory content is correctly written with the control pannel (how do you check that ?) but is changed (overwritten?) when debugged with the ide, then it could be that the ide, or the startupcode of the application initials the complete memory. (in that case with 0)
did you try to read the memory back after writing the hex file ?
next thing, after you have written your hex data into sdram, is the fpga reconfigured ? do you load a new fpga image ? if yes then the sdram conroller ip is not present during configuration and so no refresh cycle is performed during that time.