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Altera_Forum
Honored Contributor
10 years agoThanks Ted....
We have narrowed one fail on Stratix V PCIe at Gen3 X 4 to be some failure of a byte write, int writes operate fine but for some reason the byte write by NIOS II outbound to host memory turns into a 4 DWORD PCIe operation which I am not even sure is legal ... This is seen at both Gen3 X 4 and Gen1 X 4. I can either try to simulate it with a bus master replacing the NIOS II data master or as you indicate employ Signal Tap to see what transaction NIOS II sent to the PCIe TXS slave. Thanks Bob. Attached is an analyzer trace of what was supposed to be a byte write .. but I think the non contiguous byte enables is not legal.