Nios II has no sleep/idle/wfi instruction?

Most of the stuff I've done is mains powered, saving a few mW isn't worth the effort. What is more important is the throughput and latency, interrupt entry exit is typically slow (due to all the register saves), and has to be disabled for some code paths.

I'd use interrupts if the cpu had anything else to do.

To sleep in a customn instruction you'd have to feed the irq/wakup line into the custom instruction code. Not difficult, but it might need a separate interrupt enable mask (or use your own interrupt controller).

I don't know how much gets stalled by custom instructions, we have looked at directly coupled data memory during an avalon bus stall. The clock enable (address latch enable if single clock and qsys) is used to hold the data from an earlier cycle valid during the stall, so that will have fewer transitions and be lower power.